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1 1 2 3 4 8 7 6 5 cs so wp gnd vcc hold sck si 8-lead soic 1 2 3 4 8 7 6 5 cs so wp gnd vcc hold sck si 8-lead tssop 1 2 3 4 8 7 6 5 vcc hold sck si cs so wp gnd 8-lead sap bottom view features ? serial peripheral interface (spi) compatible ? supports spi modes 0 (0,0) and 3 (1,1) ? data sheet describes mode 0 operation ? low-voltage operation ? 1.8 (v cc = 1.8v to 3.6v) ? 10 mhz clock rate (2.7 ? 3.6v) ? 128-byte page mode and byte write operation supported ? block write protection ? protect 1/4, 1/2, or entire array ? write protect (wp ) pin and write disable instructions for both hardware and software data protection ? self-timed write cycle (5 ms max) ? high-reliability ? endurance: 1 million write cycles ? data retention: >40 years ? automotive grade temperature available ? lead-free/halogen-free devices ? 8-lead jedec soic, 8-lead t ssop and 8-lead sap packages ? die sales: wafer form, waffle pack, and bumped die description the AT25512 provides 524,288 bits of serial electrically-erasable programmable read only memory (eeprom) organized as 65,536 words of 8 bits each. the device is optimized for use in many industrial and commercial applicat ions where low-power and low-voltage operation are essential. the devices are available in space saving 8-lead jedec soic, 8-lead tssop and 8- lead sap packages. in addition, the entire family is available in 1.8v (1.8v to 3.6v) versions. the AT25512 is enabled through the chip select pin (cs ) and accessed via a 3-wire interface consisting of serial data input (si), serial data output (so), and serial clock (sck). all programming cycles are co mpletely self-timed, and no separate erase cycle is required before write. table 1. pin configurations pin name function cs chip select sck serial data clock si serial data input so serial data output gnd ground vcc power supply wp write protect hold suspends serial input nc no connect 5165a?seepr?1/07 spi serial eeprom 512k (65,536 x 8) AT25512 advance information
2 AT25512 5165a?seepr?1/07 block write protection is enabled by programming the status register with top ?, top ? or entire array of write protection. separate program enable and program disable instructions are provided for additional data protection. hardware da ta protection is pro- vided via the wp pin to protect against in advertent write attempts to the status register. the hold pin may be used to suspend any serial communication without resetting the serial sequence. figure 1. block diagram note: 1. this parameter is characterized and is not 100% tested. absolute maximum ratings* operating temperature ......................................? 55 c to +125 c *notice: stresses beyond those listed under ?absolute maxi- mum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other condi- tions beyond those indicated in the operational sec- tions of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. storage temperature .........................................? 65 c to +150 c voltage on any pin with respect to ground ........................................ ? 1.0v to +5.0v maximum operating voltage ............................................ 4.3v dc output current........................................................ 5.0 ma 65536x 8 table 2. pin capacitance (1) applicable over recommended operating range from t a = 25 c, f = 1.0 mhz, v cc = +3.6v (unless otherwise noted) symbol test conditions max units conditions c out output capacitance (so) 8 pf v out = 0v c in input capacitance (cs , sck, si, wp , hold )6pfv in = 0v
3 AT25512 5165a?seepr?1/07 note: 1. v il min and v ih max are reference only and are not tested. table 3. dc characteristics applicable over recommended operating range from t ai = ? 40c to +85c, v cc = +1.8v to +3.6v, v cc = +1.8v to +3.6v(unless otherwise noted) symbol parameter test condition min typ max units v cc1 supply voltage 1.8 3.6 v i cc1 supply current v cc = 3.6v at 10 mhz, so = open, read, write 5.0 7.0 ma i cc2 supply current v cc = 3.6v at 1 mhz, so = open, read, write 2.2 3.5 ma i sb1 standby current v cc = 1.8v, cs = v cc 0.2 3.0 a i sb2 standby current v cc = 2.7v, cs = v cc 0.5 3.0 a i sb3 standby current v cc = 3.6v, cs = v cc 2.0 5.0 a i il input leakage v in = 0v to v cc ? 3.0 3.0 a i ol output leakage v in = 0v to v cc , t ac = 0 c to 70 c ? 3.0 3.0 a v il (1) input low-voltage ? 1.0 v cc x 0.3 v v ih (1) input high-voltage v cc x 0.7 v cc + 0.5 v v ol1 output low-voltage 1.8v v cc 3.6v i ol = 0.15 ma 0.2 v v oh1 output high-voltage i oh = ? 100 a v cc ? 0.2 v table 4. ac characteristics applicable over recommended operating range from t ai = ? 40 c to + 85 c, v cc = as specified, cl = 1 ttl gate and 30 pf (unless otherwise noted) symbol parameter voltage min max units f sck sck clock frequency 2.7 ? 3.6 1.8 ? 3.6 0 0 10 5 mhz t ri input rise time 2.7 ? 3.6 1.8 ? 3.6 2 2 s t fi input fall time 2.7 ? 3.6 1.8 ? 3.6 2 2 s t wh sck high time 2.7 ? 3.6 1.8 ? 3.6 40 80 ns t wl sck low time 2.7 ? 3.6 1.8 ? 3.6 40 80 ns t cs cs high time 2.7 ? 3.6 1.8 ? 3.6 100 200 ns t css cs setup time 2.7 ? 3.6 1.8 ? 3.6 100 200 ns t csh cs hold time 2.7 ? 3.6 1.8 ? 3.6 100 200 ns t su data in setup time 2.7 ? 3.6 1.8 ? 3.6 10 20 ns
4 AT25512 5165a?seepr?1/07 note: 1. this parameter is ensured by characterization only. serial interface description master: the device that genera tes the serial clock. slave: because the serial clock pin (sck) is always an input, the AT25512 always operates as a slave. transmitter/receiver: the AT25512 has separate pins designated for data transmission (so) and reception (si). msb: the most significant bit (msb) is the first bit transmitted and received. serial op-code: after the device is selected with cs going low, the first byte will be received. this byte contains the op-code that defines the operat ions to be performed. invalid op-code: if an invalid op-code is received, no data will be shifted into the AT25512, and the serial output pin (so) will remain in a high impedance state until the falling edge of cs is detected again. this will re initialize the seri al communication. chip select: the AT25512 is selected when the cs pin is low. when the device is not selected, data will not be accepted via the si pin, and the serial output pin (so) will remain in a high impedance state. hold: the hold pin is used in conjunction with the cs pin to select the AT25512. when the device is selected and a serial sequence is underway, hold can be used to pause the serial communication with the master device without resetting the serial sequence. to pause, the hold pin must be brought low while the sck pin is low. to resume serial comm unication, the hold pin is brought high while the sck pin is low (sck may still toggle during hold ). inputs to the si pin will be ignored while the so pin is in the high impedance state. t h data in hold time 2.7 ? 3.6 1.8 ? 3.6 10 20 ns t hd hold setup time 2.7 ? 3.6 1.8 ? 3.6 10 20 ns t cd hold hold time 2.7 ? 3.6 1.8 ? 3.6 10 20 ns t v output valid 2.7 ? 3.6 1.8 ? 3.6 0 0 40 80 ns t ho output hold time 2.7 ? 3.6 1.8 ? 3.6 0 0 ns t lz hold to output low z 2.7 ? 3.6 1.8 ? 3.6 0 0 50 100 ns t hz hold to output high z 2.7 ? 3.6 1.8 ? 3.6 50 100 ns t dis output disable time 2.7 ? 3.6 1.8 ? 3.6 50 100 ns t wc write cycle time 2.7 ? 3.6 1.8 ? 3.6 5 5 ms endurance (1) 3.3v, 25 c, page mode 1m write cycles table 4. ac characteristics (continued) applicable over recommended operating range from t ai = ? 40 c to + 85 c, v cc = as specified, cl = 1 ttl gate and 30 pf (unless otherwise noted) symbol parameter voltage min max units
5 AT25512 5165a?seepr?1/07 write protect: the write protect pin (wp ) will allow normal read/write operations when held high. when the wp pin is brought low and wpen bit is ?1?, all write opera- tions to the status regi ster are inhibited. wp going low while cs is still low will interrupt a write to the status register . if the internal write cycl e has already been initiated, wp going low will have no effect on any write operation to the stat us register. the wp pin function is blocked when the wpen bit in the status register is ?0?. this will allow the user to install the AT25512 in a system with the wp pin tied to ground and still be able to write to the status register. all wp pin functions are enabled when the wpen bit is set to ?1?. figure 2. spi serial interface AT25512
6 AT25512 5165a?seepr?1/07 functional description the AT25512 is designed to interface directly with the synchronous serial peripheral interface (spi) of the 6800 type series of microcontrollers. the AT25512 utilizes an 8-bit instruction register. the lis t of instructions and their oper- ation codes are contained in see table 5. all instructions, addresses, and data are transferred with the msb first and start with a high-to-low cs transition. write enable (wren): the device will power-up in the write disable state when v cc is applied. all programming instructions mu st therefore be preceded by a write enable instruction. write disable (wrdi): to protect the device against inadvertent writes, the write disable instruction disables all programming modes. the wrdi instruction is indepen- dent of the status of the wp pin. read status register (rdsr): the read status register instruction provides access to the status register. the ready /busy and write enable status of the device can be determined by the rdsr instruction. similarly, the block write protection bits indicate the extent of protection employed. these bits are set by using the wrsr instruction. table 5. instruction set for the AT25512 instruction name instruction format operation wren 0000 x110 set write enable latch wrdi 0000 x100 reset write enable latch rdsr 0000 x101 read status register wrsr 0000 x001 write status register read 0000 x011 read data from memory array write 0000 x010 write data to memory array table 6. status register format bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 wpen x x x bp1 bp0 wen rdy table 7. read status register bit definition bit definition bit 0 (rdy ) bit 0 = ?0? (rdy ) indicates the device is ready. bit 0 = ?1? indicates the write cycle is in progress. bit 1 (wen) bit 1 = 0 indicates the device is not write enabled. bit 1 = ?1? indicates the device is write enabled. bit 2 (bp0) see table 8 on page 7. bit 3 (bp1) see table 8 on page 7. bits 4 ? 6 are 0s when device is no t in an inter nal write cycle. bit 7 (wpen) see table 9 on page 7. bits 0 ? 7 are ?1?s during an internal write cycle.
7 AT25512 5165a?seepr?1/07 write status register (wrsr): the wrsr instruction allows the user to select one of four levels of protection. the AT25512 is divided into four array segments. top quarter (1/4), top half (1/2), or all of the memory segments can be protected. any of the data within any selected segm ent will therefore be read only . the block write protection levels and corresponding status register control bits are shown in table 8. the three bits, bp0, bp1, and wpen are nonvol atile cells that have the same properties and functions as the regular memory cells (e.g. wren, t wc , rdsr). the wrsr instruction also allows the user to enable or disable the write protect (wp ) pin through the use of the write protect enabl e (wpen) bit. hardware write protection is enabled when the wp pin is low and the wpen bit is ?1?. hardware write protection is disabled when either the wp pin is high or the wpen bit is ?0?. when the device is hard- ware write protected, writes to the status register, including the block protect bits and the wpen bit, and the block-protected sections in the memory array are disabled. writes are only allowed to sections of the memory which are not block-protected. note: when the wpen bit is hardware write protected, it cannot be changed back to ?0?, as long as the wp pin is held low. read sequence (read): reading the AT25512 via the so pin requires the follow- ing sequence. after the cs line is pulled low to select a device, the read op-code is transmitted via the si line followed by the byte address to be read (see table 10 on page 8). upon completion, any data on the si line will be ignored. the data (d7 - d0) at the specified address is then shifted out onto the so line. if only one byte is to be read, the cs line should be driven high after the da ta comes out. the read sequence can be continued since the byte addr ess is automatically incremen ted and data will continue to be shifted out. when the high est address is reached, the address counter will roll over to the lowest address allowing the entire memory to be read in one continuous read cycle. table 8. block write protect bits level status register bits array addresses protected bp1 bp0 AT25512 00 0 none 1(1/4) 0 1 c000 - ffff 2(1/2) 1 0 8000 ? ffff 3(all) 1 1 0000 ? ffff table 9. wpen operation wpen wp wen protected blocks unprotected blocks status register 0 x 0 protected protected protected 0 x 1 protected writable writable 1 low 0 protected protected protected 1 low 1 protected writable protected x high 0 protected protected protected x high 1 protected writable writable
8 AT25512 5165a?seepr?1/07 write sequence (write): in order to program the AT25512, two separate instructions must be exec uted. first, the device must be write enabled via the write enable (wren) instruction. then a write instruction may be executed. also, the address of the memory location(s) to be programmed must be outside the protected address field location selected by the block write protection level. during an internal write cycle, all commands will be igno red except the rdsr instruction. a write instruction requires the following sequence. after the cs line is pulled low to select the device, the write op-code is transm itted via the si line followed by the byte address and the data (d7 - d0) to be progr ammed (see table 10). programming will start after the cs pin is brought high. (the low- to-high transition of the cs pin must occur during the sck low time immediately after clocking in the d0 (lsb) data bit. the ready/busy status of the device c an be determined by initiating a read status register (rdsr) instruction. if bit 0 = 1, the write cycle is still in progress. if bit 0 = 0, the write cycle has ended. only the read st atus register instruction is enabled during the write programming cycle. the AT25512 is capable of a 128-byte page wr ite operation. after each byte of data is received, the six low order address bits are in ternally incremented by one; the high order bits of the address will remain constant. if mo re than 128 bytes of data are transmitted, the address counter will roll over and the previo usly written data will be overwritten. the AT25512 is automatically returned to the writ e disable state at the completion of a write cycle. note: if the device is not write enabled (wren), the device will ignore the write instruction and will return to the standby state, when cs is brought high. a new cs fall- ing edge is required to re-initiate the serial communication. table 10. address key address AT25512 a n a 15 ? a 0
9 AT25512 5165a?seepr?1/07 timing diagrams (for spi mode 0 (0, 0)) figure 3. synchronous data timing figure 4. wren timing so v oh v ol hi-z hi-z t v valid in si v ih v il t h t su t dis sck v ih v il t wh t csh cs v ih v il t css t cs t wl t ho
10 AT25512 5165a?seepr?1/07 figure 5. wrdi timing figure 6. rdsr timing figure 7. wrsr timing cs s ck 01234567891011121314 si instruction so 76543210 data out msb high impedance 15
11 AT25512 5165a?seepr?1/07 figure 8. read timing figure 9. write timing figure 10. hold timing so sck hold t cd t hd t hz t lz t cd t hd cs
12 AT25512 5165a?seepr?1/07 AT25512 ordering information notes: 1. ?-b? denotes bulk. 2. ?-t? denotes tape and reel. soic = 4k per reel. tssop = 5k per reel. sap = 3k per reel. 3. available in waffle pack, tape and reel, and wafer form; or der as sl788 for inkless wafer form. bumped die available upon request. please contact serial interface marketing. ordering code voltage package operation range AT25512n-sh-b (1) AT25512n-sh-t (2) AT25512-th-b (1) AT25512-th-t (2) AT25512y7-yh-t (2) 1.8 1.8 1.8 1.8 1.8 8s1 8s1 8a2 8a2 8y7 lead-free/halogen-free nipdau lead finish industrial temperature (?40 c to 85 c) AT25512-w-11 (3) 1.8 die sale industrial temperature (?40 c to 85 c) package type 8s1 8-lead, 0.150" wide, plastic gull wing small outline (jedec soic) 8a2 8-lead, 4.4 mm body, plastic thin shrink small outline package (tssop) 8y7 8-lead, 6.00mm x 4.90mm body, ultra thin, dual footprint, non-leaded, small array package (sap) options ? 1.8 low-voltage (1.8v to 3.6v)
13 AT25512 5165a?seepr?1/07 packaging information 8s1 ? jedec soic 1150 e. cheyenne mtn. blvd. colorado springs, co 80906 title drawing no. r rev. note: 10/7/03 8s1 , 8-lead (0.150" wide body), plastic gull wing small outline (jedec soic) 8s1 b common dimensions (unit of measure = mm) symbol min nom max note a1 0.10 ? 0.25 these drawings are for general information only. refer to jedec drawing ms-012, variation aa for proper dimensions, tolerances, datums, etc. a 1.35 ? 1.75 b 0.31 ? 0.51 c 0.17 ? 0.25 d 4.80 ? 5.00 e1 3.81 ? 3.99 e 5.79 ? 6.20 e 1.27 bsc l 0.40 ? 1.27 ? 0? ? 8? ? top view end view side view e b d a a1 n e 1 c e1 l
14 AT25512 5165a?seepr?1/07 8a2 ? tssop 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 5/30/02 common dimensions (unit of measure = mm) symbol min nom max note d 2.90 3.00 3.10 2, 5 e 6.40 bsc e1 4.30 4.40 4.50 3, 5 a ? ? 1.20 a2 0.80 1.00 1.05 b 0.19 ? 0.30 4 e 0.65 bsc l 0.45 0.60 0.75 l1 1.00 ref 8a2 , 8-lead, 4.4 mm body, plastic thin shrink small outline package (tssop) notes: 1. this drawing is for general information only. refer to jedec drawing mo-153, variation aa, for proper dimensions, tolerances, datums, etc. 2. dimension d does not include mold flash, protrusions or gate burrs. mold flash, protrusions and gate burrs shall not exceed 0.15 mm (0.006 in) per side. 3. dimension e1 does not include inter-lead flash or protrusions. inter-lead flash and protrusions shall not exceed 0.25 mm (0.010 in) per side. 4. dimension b does not include dambar protrusion. allowable dambar protrusion shall be 0.08 mm total in excess of the b dimension at maximum material condition. dambar cannot be located on the lower radius of the foot. minimum space between protrusion and adjacent lead is 0.07 mm. 5. dimension d and e1 to be determined at datum plane h. 8a2 b side view end view top view a2 a l l1 d 1 2 3 e1 n b pin 1 indicator this corner e e
15 AT25512 5165a?seepr?1/07 8y7 - sap 1150 e. cheyenne mtn. blvd. colorado springs, co 80906 title drawing no. r rev. 8y7 , 8-lead (6.00 x 4.90 mm body) ultra-thin soic array package (utsap) y7 b 8y7 10/13/05 common dimensions (unit of measure = mm) symbol min nom max note a ? ? 0.60 a1 0.00 ? 0.05 d 5.80 6.00 6.20 e 4.70 4.90 5.10 d1 3.30 3.40 3.50 e1 3.90 4.00 4.10 b 0.35 0.40 0.45 e 1.27 typ e1 3.81 ref l 0.50 0.60 0.70 d1 pin 1 id e1 l b e1 e pin 1 index area a e d a1 a
16 AT25512 5165a?seepr?1/07 revision history doc. rev. date comments 5165a 1/2007 initial document release.
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